The present invention relates to a technique for manufacturing a semiconductor integrated circuit device, and particularly to a technique effectively applied to manufacture of a semiconductor integrated circuit device having a so-called complementary MISFET with a dual-gate structure (Dual-gate type CMOSFET), in which a gate electrodes of n-channel type MISFET and a gate electrode of p-channel type MISFET are composed of silicon films of different conductivity types.
The semiconductor device in which a circuit is composed of a complementary MISFET has recently widely adopted a dual-gate structure in which a gate electrode of n-channel type MISFET is composed of an n-type poly-silicon film and a gate electrode of p-channel type MISFET is composed of a p-type poly-silicon film.
This is due to the following reason. Namely, in the case where both gate electrodes of n-channel type MISFET and p-channel type MISFET are composed of n-type poly-silicon films similarly to conventional semiconductor devices, the p-channel type MISFET has a buried channel structure and short channel effects become prominent at the time of miniaturizing the devices, so that it is necessary to adopt the dual-gate structure even if the number of steps is increased and to promote miniaturization of the devices by suppressing the short channel effects.
Japanese Patent Laid-Open No. 11-195713 (hereinafter “Patent Document 1”), Japanese Patent Laid-Open No. 9-260509 (“Patent Document 2”), and Japanese Patent Laid-Open No. 10-50857 (“Patent Document 3”) teach a polycide's dual-gate structure in which the gate electrode of n-channel type MISFET is composed of a laminated film of an n-type poly-silicon film and a tungsten silicide film and the gate electrode of p-channel type MISFET is composed of a laminated film of a p-type poly-silicon film and a tungsten silicide film, and then disclose a technique in which respective impurities in the n-type poly-silicon film and the p-type poly-silicon film in the polycide dual-gate structure are prevented from performing mutual diffusion through the tungsten silicide film with large diffusion coefficient.
In Patent Document 1, the gate electrode of n-channel type MISFET and the gate electrode of p-channel type MISFET are separated on a field dielectric film, and a portion located above the field dielectric film and in an insulating film covering the gate electrodes is provided with a groove, and the above-mentioned gate electrodes are connected to each other through a conductive layer such as tungsten embedded in an inside of the groove. Meanwhile, also in Patent Documents 2 and 3, the gate electrodes are electrically connected to each other through a conductive layer located on the field dielectric film, but the n-type poly-silicon film and the p-type poly-silicon film are not separated and only the tungsten silicide film is separated on the field dielectric film.
Japanese Patent Laid-Open No. 7-161826 (“Patent Document 4”) discloses a technique for preventing mutual diffusion of respective impurities in a p-type gate electrode and an n-type gate electrode in a CMOS device adopting a dual-gate structure. The forming method for a dual-gate electrode, as disclosed in this gazette, is such that a polysilicon film is first deposited on a silicon substrate and an aperture is formed in the polysilicon film located on an isolation region and thereby the respective polysilicon films on a p well and an n well are separated from each other. Next, boron is ion-implanted into the polysilicon film located on the p well and arsenic is ion-implanted into the polysilicon film located on the n well, and thereafter a tungsten film is deposited on the entire surface of a substrate to connect the n-type polysilicon film and the p-type polysilicon film by the tungsten film.
In the n-type gate electrode and the p-type gate electrode that have been manufactured by the above-described method, the mutual diffusion of the impurities can be prevented since the n-type polysilicon film and the p-type polysilicon film are not in direct contact with each other.
Japanese Patent Laid-Open No. 2001-210725 (“Patent Document 5”) discloses a semiconductor device of dual-gate structure in which a contact is formed in a boundary between an n-type gate electrode and a p-type gate electrode and a conductive material made of refractory metal or silicide thereof is buried in the contact.
According to the above-mentioned dual-gate structure, even when a high-resistance region is formed on the boundary between the n-type gate electrode and the p-type gate electrode owing to the mutual diffusion of the impurities, electric connection is maintained by the conductive material buried in the contact, so that circuit defect in which the electric connection between the gate electrodes is lost can be prevented.
Development of a SoC (System on Chip) in which an operation circuit, a memory circuit, a logic circuit, an analog circuit, and a RF circuit, etc. are integrated onto a single semiconductor chip has recently been promoted as a technique for realizing miniaturization and high performance of the system.
In the SoC, the above-described dual-gate structure is adopted to meet the needs of the higher performance of the system. Also, when a DRAM (Dynamic Random Access Memory) is mounted on a portion of the memory circuit, a polycide film in which a tungsten silicide film is laminated on an upper portion of a poly-silicon film is adopted as a low-resistance gate-electric material coping with a heat treatment performed at high temperature in forming a capacitor of a memory cell.